1. Field of the Invention
The present invention relates to the field of circuit design and, more particularly, to incremental implementation flow for programmable logic devices.
2. Description of the Related Art
Incremental Implementation Flow (incremental flow) refers to a methodology for processing circuit designs in a manner that attempts to reuse prior implementation results for unchanging portions of the design. Incremental flow typically is used when an incremental change is made to a circuit design intended for use on a target programmable logic device (PLD), such as a field programmable gate array (FPGA). In general, an incremental change can be one that affects one or more portions of the circuit design. Typically, an incremental change neither significantly alters the size of the circuit design nor adversely affects the timing of the circuit design as a whole. Still, an incremental change can be more substantive in that timing may be adversely affected. Examples of incremental design changes can include, but are not limited to, changes to state machines, control logic, or the addition of registers intended to improve performance of the circuit design.
Incremental flow provides several benefits, making it a useful and desirable circuit design technique. One such benefit is that achieving verified results can be accomplished more rapidly. Results from a prior implementation flow likely have undergone significant testing and/or verification. In depth analysis of this sort is critical to ensuring a reliable circuit design. Repeating such analysis each time the circuit design undergoes a minor, or incremental, change can be cumbersome and time consuming, particularly since significant portions of the circuit design remain unchanged. Re-use of previously tested portions of the circuit design can reduce the time needed to arrive at a verified design solution.
Another benefit is that incremental flow supports a “divide and conquer” approach to circuit design. Creating a circuit design that conforms to an established design goal, for example in terms of timing requirements, power consumption, and the like, can be exceedingly difficult and time consuming. In such cases, it is useful to “lock” one or more particularly complex or troublesome portions of the circuit design to prevent further changes to those portions as other sections of the circuit design continue to evolve. The designer can direct his or her attention to the unfinished, evolving portions of the circuit design.
One technique for performing incremental flow is referred to as the guide technique. The guide technique utilizes results from a prior implementation flow, in reference to synthesis, translation, mapping, packing, placing, and routing, for the circuit design. These results, referred to as guide files, can be the output files from one or more phases of a prior implementation pass for the circuit design. The guide files are used during incremental flow to guide implementation of unchanged portions of the circuit design.
More particularly, the guide technique performs correlation among the thousands of leaf blocks in the implementation hierarchy. The leaves of the implementation hierarchy correspond to the logical elements that will be programmed onto the look-up-tables, flip-flops, and other circuit functions on the target FPGA. The hierarchy is created by circuit design implementation tools to enable efficient processing. For example, certain user constraints become levels of hierarchy.
Because synthesis, mapping, and packing are very sensitive to source code changes, the resulting leaf blocks may differ significantly for even a small change to the hardware description language (HDL), or source code, description of the circuit design. For example, a small source code change may overfill a particular look-up table, thereby producing a change that permeates throughout the circuit design. In that case, leaf-level correlation would be unable to match any of the affected blocks. Once correlation has been performed, the guide technique uses the existing infrastructure of the electronic design automation tool for handling circuit design constraints to instruct the tools to reuse the matched logic. Processing and evaluation of constraints can be very time-consuming. As a result, the guide technique often is slower than the initial implementation run.
One disadvantage of conventional incremental flow techniques, however, is that such techniques do not leverage hierarchy. Hierarchy refers to the ordered, or ranked, arrangement of modules of a circuit design that naturally occurs in most HDLs. The lack of support for hierarchy often makes incremental flow more complex. In illustration, conventional incremental flows do not allow the user to specify whether the implementation(s) of any set of module instances at any level of the design hierarchy should be reused. Conventional flows preclude the designer from specifying that modules in the same hierarchy should be reused. In consequence, the designer has little control over the granularity of reuse of portions of the circuit design, since reuse occurs only for the module instances directly under the root module of the circuit design.
Another disadvantage of conventional incremental flow techniques is that a designer must control each phase of the incremental flow, i.e. synthesis, translation, mapping, packing, placement, and routing, separately. For example, if a given module of the HDL representation of the circuit design is to be incrementally synthesized, a directive must be provided to the synthesis tool specifying the particular module to be incrementally synthesized. The circuit designer then must provide a similar directive to the translation tool, then to the mapping tool, etc., on through each phase of implementation.
Still another disadvantage is that re-use of a particular portion of a circuit design, i.e. a particular source module, still requires physically floorplanning the module. Floorplanning is a complex task that requires considerable skill on the part of the circuit designer to achieve high quality results. Without such skill, a degraded circuit design often results. Additionally, because floorplanning is performed a priori, a significant amount of time is required before a determination can be made as to whether incremental flow is even desired.
It would be beneficial to provide a technique that facilitates incremental flow which overcomes the limitations described above.